Recently, semiconductor devices such as a LSI or the like have been required to have higher density in order to meet requirements for reducing the mounting space or for improving the processing rate. As an example of a technology that achieves the higher density, there has been known a multilayer wiring technology of manufacturing a multilayer substrate, such as a three-dimensional LSI or the like, by stacking multiple wiring substrates.
According to the multilayer wiring technology, a through-via-hole in which a conductive material such as copper (Cu) is buried is typically formed to penetrate each wiring substrate in order to obtain electrical connection between the wiring substrates.
When preparing the wiring substrate, Cu is used as a conductive material and is buried in a recess of the substrate. For this purpose, a barrier layer as a Cu diffusion barrier film needs to be formed within the recess, and a seed film needs to be formed on the barrier film by electroless Cu plating. Accordingly, a wiring volume of a wiring layer may be reduced or a void may be formed in the buried Cu. Meanwhile, there has been also proposed a method of burying, instead of Cu, a Ni-based metal within the recess of the substrate by an electroless plating and using the Ni-based metal as the wiring layer.
When burying the Ni-based metal within the recess of the substrate, however, the Ni-based metal layer may be formed at the outside of the recess as well. In such a case, the portion of the Ni-based metal layer formed the outside of the recess needs to be removed later by using a chemical mechanical polishing process.
Patent Document 1: Japanese Patent Laid-open Publication No. 2010-185113